The design process for a new IC includes several steps using automated EDA tools. During initial schematic design, the designer identifies a set of functions to include in the design, along with their standard delays. The designer uses computer implemented tools to perform functional simulation, to ensure that the design performs its intended function(s). Before the schematic design is laid out, the designer performs a pre-simulation. The pre-simulation takes into account device and cell characteristics, to provide an estimate of circuit performance (i.e., performance in both analog and digital designs, including timing performance in digital designs). If the design meets circuit performance requirements in the pre-simulation, the designer initiates the floorplan and layout phases, to generate the actual IC layout, using the place and route engine of the EDA tool. If the pre-simulation identifies significant performance issues, the designer modifies the design before proceeding to layout.
Following the layout process, the user verifies the design by using the EDA tools to perform design rule checks (DRC), layout versus schematic (LVS) checks, and RC extraction. The RC extraction tool takes into account the layout of the conductive (e.g., metal) lines of the interconnect layers generated by the router and computes parasitic resistance and capacitance elements associated with each conductive line. Then a post-simulation verifies circuit performance, taking into account the parasitic resistance and capacitance elements, in addition to the device and cell characteristics.
With the advent of advanced technology nodes having geometries of 40 nanometers and smaller, the delays associated with the interconnect conductive lines become more significant, and will surpass the device and cell characteristics as the bottleneck in IC design.